HY5DU283222BF-33 - 128M(4Mx32) GDDR SDRAM - Hynix Semiconductor
• The Hynix HY5DU283222BF(P) guarantee until
200MHz speed at DLL_off condition
• 2.5V VDD and VDDQ wide range max power supply
supports
• All inputs and outputs are compatible with SSTL_2
interface
• 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Write mask byte controls by DM (DM0 ~ DM3)
• Programmable /CAS Latency 5 / 4 / 3 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 4096 refresh cycles / 32ms
• Half strength and Matched Impedance driver option
controlled by EMRS
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