HY57V561620BT-H

4 Banks x 4M x 16Bit Synchronous DRAM

 

 

FEATURES

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin 

pitch

All inputs and outputs referenced to positive edge of system clock

Data mask function by UDQM, LDQM

Internal four banks operation

Auto refresh and self refresh

8192 refresh cycles / 64ms 

Programmable Burst Length and Burst Type

 - 1, 2, 4, 8 or Full page for Sequential Burst

 - 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Ambient Temperature : - 40 ~ 85 °C

 

 

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