YGV630 YGV630-B YGV630-BZ -- Advanced Video Display Processor 8
Features
CPU Interface
・ 16 bits or 32 bits Data Bus width selection.
・ Byte-write operation using WR3-0_N pin.
・ Supports data access in both big-endian and little-endian formats.
・ Direct drawing to the entire video memory spaces from CPU.
・ Prepares an interrupt pin.
・ Bus Wait and Bus Ready signal controls.
Clock
・ A PLL for system clock generation.
・ A PLL for dot clock generation.
Analog Video Input
・ 12-channel analog video input.
・ Supports Composite Video, S-Video, and Component Video Input. (Supports NTSC(M, J, 4.43), PAL(B, D, G, H, I, M, N, CN).
・ Supports analog RGB input (progressive scan of a dot clock 10 MHz or less only).
・ Up to four analog RGBs.
Digital Video Input
・ Supports ITU-R BT.656.
・ Supports RGB (18 bits) (A dot clock of 75MHz or lower).
・ Supports YCrCb(16 bits). (A dot clock of 75MHz or lower)
・ 1-channel digital RGB (18 bits) input, 1-channel YCrCb(16 bits), or 2-channel ITU-R BT.656.
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