74LVC373APW

 74LVC373APW  -Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

FEATURES

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

• Supply voltage range of 2.7V to 3.6V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• Direct interface with TTL levels

• High impedance when VCC = 0V

DESCRIPTION

The 74LVC373A is a high-performance, low-power, low-voltage,

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families.

Inputs can be driven from either 3.3V or 5V devices. In 3-State

operation, outputs can handle 5V. This feature allows the use of

these devices as translators in a mixed 3.3V/5V environment.

The 74LVC373A is an octal D-type transparent latch featuring

separate D-type inputs for each latch and 3-State outputs for

bus-oriented applications. A latch enable (LE) input and an output

enable (OE) input are common to all internal latches.

 The ’373’ consists of eight D-type transparent latches with 3-State

true outputs. When LE is HIGH, data at the Dn inputs enters the

latches. In this condition, the latches are transparent, i.e. a latch

output will change each time its corresponding D-input changes.

When LE is LOW, the latches store the information that was present

at the D-inputs one setup time preceding the HIGH-to-LOW

transition of LE. When OE is LOW, the contents of the eight latches

are available at the outputs. When OE is HIGH, the outputs go to the

high impedance OFF-state. Operation of the OE input does not

affect the state of the latches.

The ’373’ is functionally identical to the ’573’, but the ’573’ has a

different pin arrangement.

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