Features
■ Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
■ 333 MHz Clock for High Bandwidth
■ 2-word Burst on all Accesses
■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 666 MHz) at 333 MHz
■ Two Input Clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
■ Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports
■ Separate Port Selects for Depth Expansion
■ Synchronous internally Self-timed Writes
■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
■ Operates similar to QDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 Configurations
■ Full Data Coherency, providing Most Current Data
■ Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
❐ Supports both 1.5V and 1.8V IO supply
■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ Variable Drive HSTL Output Buffers
■ JTAG 1149.1 Compatible Test Access Port
■ Phase Locked Loop (PLL) for Accurate Data Placement
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【買家必讀】：電子元器件是專業型的產品，技術含量較高，本身可能存在多種品牌，後輟與封裝，可能導致參數與性能的差異，如有不慎，很有可能導致元器件購買錯誤，為了更好的解決您的問題，所以請您務必在下单前，將產品的封裝、後綴告訴我們。以便我們能準確迅速的为您查询。
由于客户采购批量与样品的价格不同，网上无法统一注明，请您把采购型号通过页面旺旺或客服QQ401799895或拨打国内销售部电话：0755-83957301，由客服人员为您报价；有时元件厂商价格稍许变动，本公司未能及时调整，如您觉得售价稍高，请与我们说明并适当议价，我们会根据市场情况给您相应的折扣，我们保证提供最市场最优势的价格最好元器件；感谢支持（所售元件均无含税，需开普票7%和增值票17%的客户请说明）
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