SAA7111AHZ
Enhanced Video Input Processor EVIP
FEATURES
Four analog inputs, internal analog source selectors,
e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)
Two analog preprocessing channels
Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel
Switchable white peak control
Two built-in analog anti-aliasing filters
Two 8-bit video CMOS analog-to-digital converters
On-chip clock generator
Line-locked system clock frequencies
Digital PLL for horizontal-sync processing and clock
generation
Requires only one crystal (24.576 MHz) for all standards
Horizontal and vertical sync detection
Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards
Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N,
NTSC 4.43, NTSC-Japan and SECAM
User programmable luminance peaking or aperture
correction
Cross-colour reduction for NTSC by chrominance comb
filtering
PAL delay line for correcting PAL phase errors
Real time status information output (RTCO)
Brightness Contrast Saturation (BCS) control on-chip
The YUV (CCIR-601) bus supports a data rate of:
864 × fH = 13.5 MHz for 625 line sources
858 × fH = 13.5 MHz for 525 line sources.
Data output streams for 16, 12 or 8-bit width with the
following formats:
YUV 4 : 1 : 1 (12-bit)
YUV 4 : 2 : 2 (16-bit)
YUV 4 : 2 : 2 (CCIR-656) (8-bit)
RGB (5, 6, and 5) (16-bit) with dither
RGB (8, 8, and 8) (24-bit) with special application.
Odd/even field identification by a non interlace CVBS
input signal
Fix level for RGB output format during horizontal
blanking
720 active samples per line on the YUV bus
One user programmable general purpose switch on an
output pin
Built-in line-21 text slicer
A 27 MHz Vertical Blanking Interval (VBI) data bypass
programmable by I2C-bus for INTERCAST applications
Power-on control
Two via I2C-bus switchable outputs for the digitized
CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)
Chip enable function (reset for the clock generator and
power save mode up from chip version 3)
Compatible with memory-based features (line-locked
clock)
Boundary scan test circuit complies with the
‘IEEE Std. 1149.1 − 1990’ (ID-Code = 0 F111 02 B)
I2C-bus controlled (full read-back ability by an external
controller)
Low power (<0.5 W), low voltage (3.3 V), small package
(LQFP64)
5 V tolerant digital I/O ports.
2 APPLICATIONS
Desktop/Notebook (PCMCIA) video
Multimedia
Digital television
Image processing
Video phone
Intercast.
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